In response to a recent growing demand for a higher performance and lower power consumption of digital devices, a multi-core configuration in which a plurality of processor cores (hereinafter, each referred to as just a “core”) is mounted in a large scale integration (LSI) has been drawing attention. A development of such a multi-core configuration based LSI has also become an important technology in real-time systems or the like aiming at system control.
Methods for this multi-core system are roughly classified into a symmetric multi-processing (SMP) method and an asymmetric multi-processing (AMP) method.
In the SMP method, task switching is performed in accordance with a situation of an available capability of each of cores, a priority of each of tasks currently being executed, and the like, and each of tasks can be executed on any one of the cores. For this reason, it becomes possible to implement an automatic load distribution, so that a performance of the whole system is enhanced. Nevertheless, such an automatic load distribution makes it difficult to grasp a real-time performance beforehand, and thus, it is difficult to apply the SMP method to a real-time system.
Meanwhile, the AMP method is based on a function distribution type configuration in which each of tasks is executed on its specific core. For this reason, the AMP method is suitable for a system, such as a real-time system for which it is important to be able to grasp behaviors of the system beforehand, or an embedded system in which there are restrictions on cores each connected to specific hardware.
In a multi-core system employing such an AMP method, its performance differs depending on to which of cores each of tasks is allocated. For this reason, in such a multi-core system employing the AMP method, it is necessary to search various task allocations and determine an optimum task allocation so that the multi-core system can be placed in an optimum operation state.
Hereinbefore, description has been made by providing a multi-core system employing the AMP method as an example. The above description is generally applicable to not only a multi-core system employing the AMP method but also a multi-core system employing a function distribution type method in which tasks are allocated to individual tasks on a fixed basis.
In Japanese Unexamined Patent Application Publication No. 2007-264734 (hereinafter, referred to as “patent literature 1 (PTL 1)”, there has been disclosed a technology for a tuning support device which enables efficient software tuning for a multi-core processor provided with a plurality of cores. FIG. 21 illustrates a configuration of a tuning support device disclosed in PTL 1.
In the tuning support device, first, a granularity information acquiring unit 201 acquires information related to granularity allocated to each of cores (hereinafter, this information being referred to “granularity information”). This “granularity” is a unit of processing performed by, for example, a processor, and is a generic term representing a scale of a task, a function, or further, processes constituting a function.
A structure information generating unit 204 calculates a total appearance number for each of tasks or for each of functions included in tasks on the basis of the acquired granularity information, and generates information related to the calculated total appearance number (hereinafter, this information being referred to as “structure information”).
A dependency information generating unit 206 generates information related to dependencies on other tasks or other functions (hereinafter, this information being referred to as “dependency information”) for each of tasks or for each of functions included in tasks, on the basis of the acquired granularity information. An output unit 203 outputs these kinds of information.
Through this configuration, the tuning support device can efficiently analyze and manage the structure information for use in a load distribution. Though the use of information resulting from this analysis, for a multi-core processor, tasks are allocated to individual cores such that a processing performance of the multi-core system is enhanced.